From 47a8445c946e3792247fcf818c6e60ae72693f5c Mon Sep 17 00:00:00 2001 From: Thomas Munro Date: Tue, 30 Jul 2024 11:01:26 +1200 Subject: [PATCH] Fix x86 architecture detection on MSVC. We were looking for __x86_64__, but MSVC calls it _M_AMD64. Therefore we were mapping pg_{read,write}_barrier() to expensive pg_memory_barrier() instead of pg_compiler_barrier(), and not using the intended spinlock delay primitive. A couple of other places missed it as well. The problem probably exists for _M_IX86 (32 bit) too; this is untested due to lack of 32 bit Windows CI, but that macro was already used in our tree so it seems safe to use it in new places. Back-patch to all supported releases. Reviewed-by: Heikki Linnakangas Discussion: https://postgr.es/m/CA%2BhUKGKAf_i6w7hB_3pqZXQeqn%2BixvY%2BCMps_n%3DmJ5HAatMjMw%40mail.gmail.com --- contrib/pgcrypto/crypt-blowfish.c | 4 ++-- src/include/port/atomics.h | 3 ++- src/include/port/atomics/arch-x86.h | 2 +- src/port/pg_crc32c_sse42.c | 2 +- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/contrib/pgcrypto/crypt-blowfish.c b/contrib/pgcrypto/crypt-blowfish.c index 5a1b1e1009..c34e66b2f7 100644 --- a/contrib/pgcrypto/crypt-blowfish.c +++ b/contrib/pgcrypto/crypt-blowfish.c @@ -38,10 +38,10 @@ #include "px-crypt.h" #include "px.h" -#ifdef __i386__ +#if defined(__i386__) || defined(_M_IX86) #define BF_ASM 0 /* 1 */ #define BF_SCALE 1 -#elif defined(__x86_64__) +#elif defined(__x86_64__) || defined(_M_AMD64) #define BF_ASM 0 #define BF_SCALE 1 #else diff --git a/src/include/port/atomics.h b/src/include/port/atomics.h index f6fa432d2d..ec59745168 100644 --- a/src/include/port/atomics.h +++ b/src/include/port/atomics.h @@ -65,7 +65,8 @@ */ #if defined(__arm__) || defined(__arm) || defined(__aarch64__) #include "port/atomics/arch-arm.h" -#elif defined(__i386__) || defined(__i386) || defined(__x86_64__) +#elif defined(__i386__) || defined(__i386) || defined(_M_IX86) || \ + defined(__x86_64__) || defined(_M_AMD64) #include "port/atomics/arch-x86.h" #elif defined(__ppc__) || defined(__powerpc__) || defined(__ppc64__) || defined(__powerpc64__) #include "port/atomics/arch-ppc.h" diff --git a/src/include/port/atomics/arch-x86.h b/src/include/port/atomics/arch-x86.h index 2a8eca30fc..4ecf540d12 100644 --- a/src/include/port/atomics/arch-x86.h +++ b/src/include/port/atomics/arch-x86.h @@ -113,7 +113,7 @@ pg_spin_delay_impl(void) { __asm__ __volatile__(" rep; nop \n"); } -#elif defined(_MSC_VER) && defined(__x86_64__) +#elif defined(_MSC_VER) && defined(_M_AMD64) #define PG_HAVE_SPIN_DELAY static __forceinline void pg_spin_delay_impl(void) diff --git a/src/port/pg_crc32c_sse42.c b/src/port/pg_crc32c_sse42.c index 7f88c11480..9a87070853 100644 --- a/src/port/pg_crc32c_sse42.c +++ b/src/port/pg_crc32c_sse42.c @@ -32,7 +32,7 @@ pg_comp_crc32c_sse42(pg_crc32c crc, const void *data, size_t len) * and performance testing didn't show any performance gain from aligning * the begin address. */ -#ifdef __x86_64__ +#if defined(__x86_64__) || defined(_M_AMD64) while (p + 8 <= pend) { crc = (uint32) _mm_crc32_u64(crc, *((const uint64 *) p)); -- 2.39.2